277 lines
10 KiB
C
277 lines
10 KiB
C
#include"cpu.h"
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#include"ram.h"
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// Create new cpu_t object with
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// default values
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cpu_t*cpu_init(void)
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{
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cpu_t*cpu=new(cpu_t);
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memset(cpu,0,sizeof(cpu_t));
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return cpu;
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}
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// Increment PC and return (does not
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// reference RAM)
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uint16_t cpu_fetch(cpu_t*cpu)
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{
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return cpu->pc+=1;
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}
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// Compare
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void cpu_cmp(cpu_t*cpu,uint8_t x,uint8_t y)
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{
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cpu->sr.bits.z=(x-y)==0;
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cpu->sr.bits.c=(x<y);
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}
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// Push byte, dec cpu SP
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void cpu_push(cpu_t*cpu,ram_t*ram,uint8_t d)
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{
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ram->ram[--cpu->sp]=d;
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}
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// Push byte, dec cpu SP
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void cpu_pull(cpu_t*cpu,ram_t*ram,uint8_t*d)
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{
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*d=ram->ram[cpu->sp++];
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}
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// Push word, dec cpu SP
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void cpu_push16(cpu_t*cpu,ram_t*ram,uint16_t d)
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{
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cpu->sp-=2;
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ram->ram[cpu->sp+1]=(uint8_t)(d>>8);
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ram->ram[cpu->sp]=(uint8_t)(d&0xff);
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}
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// Pull word, inc cpu SP
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void cpu_pull16(cpu_t*cpu,ram_t*ram,uint16_t*d)
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{
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*d=(ram->ram[cpu->sp]|(ram->ram[cpu->sp+1]<<8));
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cpu->sp+=2;
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}
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// Increment cpu->a by x (for sequence point)
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uint8_t cpu_adc(cpu_t*cpu,uint8_t x)
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{
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return cpu->a+=x;
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}
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// Increment cpu->a by x (for sequence point)
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uint8_t cpu_sbc(cpu_t*cpu,uint8_t x)
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{
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return cpu->a-=x;
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}
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// Assign x to cpu->a (for sequence point)
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uint8_t cpu_assign(cpu_t*cpu,uint8_t x)
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{
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return cpu->a=x;
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}
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// Execute next instruction in RAM
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// through CPU
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void cpu_exec(cpu_t*cpu,ram_t*ram)
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{
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switch(ram->ram[cpu->pc])
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{
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// Set 'mode' to main cpu
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#define __cpu cpu
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// Move/load/transfer ---
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// Load a
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case 0xA1: lda( deref( deref( fetch() + cpu->x ) ) ); sr_nz(cpu->a); incpc(); break;
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case 0xB1: lda( deref( deref( fetch() + cpu->y ) ) ); sr_nz(cpu->a); incpc(); break;
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case 0xA5: lda( deref( fetch() ) ); sr_nz(cpu->a); incpc(); break;
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case 0xA9: lda( fetch() ); sr_nz(cpu->a); incpc(); break;
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case 0xAD: lda( deref( fetch16() ) ); sr_nz(cpu->a); incpc(); break;
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case 0xB5: lda( deref( fetch() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0xB9: lda( deref( fetch16() + cpu->y ) ); sr_nz(cpu->a); incpc(); break;
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case 0xBD: lda( deref( fetch16() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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// Store a: Do not dereference
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case 0x85: sta( fetch() ); incpc(); break;
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case 0x95: sta( fetch() + cpu->x ); incpc(); break;
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case 0x8D: sta( fetch16() ); incpc(); break;
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case 0x9D: sta( fetch16() + cpu->x ); incpc(); break;
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case 0x99: sta( fetch16() + cpu->y ); incpc(); break;
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// TODO Verify these are correct
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case 0x81: sta( fetch() + cpu->x ); incpc(); break;
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case 0x91: sta( fetch() + cpu->y ); incpc(); break;
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// Store x
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case 0x86: stx( fetch() ); incpc(); break;
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case 0x96: stx( fetch() + cpu->y ); incpc(); break;
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case 0x8E: stx( fetch16() ); incpc(); break;
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// Load x
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case 0xA2: ldx( fetch() ); sr_nz(cpu->x); incpc(); break;
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case 0xA6: ldx( deref( fetch() ) ); sr_nz(cpu->x); incpc(); break;
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case 0xB6: ldx( deref( fetch() + cpu->y ) ); sr_nz(cpu->x); incpc(); break;
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case 0xAE: ldx( deref( fetch16() ) ); sr_nz(cpu->x); incpc(); break;
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case 0xBE: ldx( deref( fetch16() + cpu->y) ); sr_nz(cpu->x); incpc(); break;
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// Store y
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case 0x84: sty( fetch() ); incpc(); break;
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case 0x94: sty( fetch() + cpu->y ); incpc(); break;
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case 0x8C: sty( fetch16() ); incpc(); break;
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// Load y
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case 0xA0: ldy( fetch() ); sr_nz(cpu->y); incpc(); break;
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case 0xA4: ldy( deref( fetch() ) ); sr_nz(cpu->y); incpc(); break;
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case 0xB4: ldy( deref( fetch() + cpu->x ) ); sr_nz(cpu->y); incpc(); break;
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case 0xAC: ldy( deref( fetch16() ) ); sr_nz(cpu->y); incpc(); break;
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case 0xBC: ldy( deref( fetch16() + cpu->x) ); sr_nz(cpu->y); incpc(); break;
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// Transfer
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case 0xA8: ldy( cpu->a ); sr_nz(cpu->a); incpc(); break;
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case 0xAA: ldx( cpu->a ); sr_nz(cpu->a); incpc(); break;
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case 0xBA: ldx( cpu->sp ); sr_nz(cpu->x); incpc(); break;
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case 0x8A: lda( cpu->x ); sr_nz(cpu->a); incpc(); break;
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case 0x9A: cpu->sp = cpu->x; sr_nz(cpu->x); incpc(); break;
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case 0x98: lda( cpu->y ); sr_nz(cpu->a); incpc(); break;
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case 0x48: push( cpu->a ); incpc(); break;
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case 0x68: pull( &cpu->a ); incpc(); break;
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// Arithmetic ---
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// TODO Check ADC for DECIMAL FLAG for conditional behavior
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// TODO Fix C + V SR flags for these
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case 0x65: adc( deref( fetch() ) ); sr_nz(cpu->a); incpc(); break;
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case 0x69: adc( fetch() ); sr_nz(cpu->a); incpc(); break;
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case 0x75: adc( deref( fetch() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0x6D: adc( deref( fetch16() ) ); sr_nz(cpu->a); incpc(); break;
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case 0x7D: adc( deref( fetch16() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0x79: adc( deref( fetch16() + cpu->y ) ); sr_nz(cpu->a); incpc(); break;
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// TODO Verify these are correct (use ind() )
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case 0x61: adc( deref( fetch() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0x71: adc( deref( fetch() + cpu->y ) ); sr_nz(cpu->a); incpc(); break;
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// SBC
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case 0xE5: sbc( deref( fetch() ) ); sr_nz(cpu->a); incpc(); break;
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case 0xE9: sbc( fetch() ); sr_nz(cpu->a); incpc(); break;
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case 0xF5: sbc( deref( fetch() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0xED: sbc( deref( fetch16() ) ); sr_nz(cpu->a); incpc(); break;
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case 0xFD: sbc( deref( fetch16() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0xF9: sbc( deref( fetch16() + cpu->y ) ); sr_nz(cpu->a); incpc(); break;
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// TODO Verify these are correct
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case 0xE1: sbc( deref( deref( fetch() + cpu->x ) ) ); sr_nz(cpu->a); incpc(); break;
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case 0xF1: sbc( deref( deref( fetch() + cpu->y ) ) ); sr_nz(cpu->a); incpc(); break;
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// INC/DEC
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case 0xE6: ram->ram[ fetch() ] += 1; incpc(); break;
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case 0xF6: ram->ram[ fetch() + cpu->x ] += 1; incpc(); break;
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case 0xEE: ram->ram[ fetch16() ] += 1; incpc(); break;
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case 0xFE: ram->ram[ fetch16() + cpu->x ] += 1; incpc(); break;
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case 0xC8: cpu-> y += 1; incpc(); sr_nz(cpu->y); break;
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case 0xE8: cpu-> x += 1; incpc(); sr_nz(cpu->x); break;
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// Bitwise ---
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// AND
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case 0x29: and( fetch() ); sr_nz(cpu->a); incpc(); break;
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case 0x25: and( deref( fetch() ) ); sr_nz(cpu->a); incpc(); break;
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case 0x35: and( deref( fetch() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0x2D: and( deref( fetch16() ) ); sr_nz(cpu->x); incpc(); break;
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case 0x3D: and( deref( fetch16() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0x39: and( deref( fetch16() + cpu->y ) ); sr_nz(cpu->a); incpc(); break;
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case 0x21: and( deref( deref( fetch() + cpu->x ) ) ); sr_nz(cpu->a); incpc(); break;
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case 0x31: and( deref( deref( fetch() + cpu->y ) ) ); sr_nz(cpu->a); incpc(); break;
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// EOR
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// TODO Check if accumulator is changed, or memory
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// TODO Verify 0x4D onward work correctly
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case 0x49: eor( fetch() ); incpc(); break;
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case 0x45: eor( deref( fetch() ) ); incpc(); break;
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case 0x55: eor( deref( fetch() + cpu->x ) ); incpc(); break;
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case 0x4D: eor( deref( fetch16() ) ); incpc(); break;
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case 0x5D: eor( deref( fetch16() + cpu->x ) ); incpc(); break;
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case 0x59: eor( deref( fetch16() + cpu->y ) ); incpc(); break;
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case 0x41: eor( deref( deref( fetch() + cpu->x ) ) ); incpc(); break;
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case 0x51: eor( deref( deref( fetch() + cpu->y ) ) ); incpc(); break;
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// ORA
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case 0x09: ora( fetch() ); incpc(); break;
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case 0x05: ora( deref( fetch() ) ); incpc(); break;
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case 0x15: ora( deref( fetch() + cpu->x ) ); incpc(); break;
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case 0x0D: ora( deref( fetch16() ) ); incpc(); break;
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case 0x1D: ora( deref( fetch16() + cpu->x ) ); incpc(); break;
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case 0x19: ora( deref( fetch16() + cpu->y ) ); incpc(); break;
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case 0x01: ora( deref( deref( fetch() + cpu->x ) ) ); incpc(); break;
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case 0x11: ora( deref( deref( fetch() + cpu->y ) ) ); incpc(); break;
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// BIT
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case 0x24: sr_nz( cpu->a & deref( imm() ) ); incpc(); break;
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case 0x2C: sr_nz( cpu->a & deref( imm16() ) ); incpc(); break;
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// Clear SR flags
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case 0x18: cpu->sr.bits.c=0; incpc(); break;
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case 0xD8: cpu->sr.bits.d=0; incpc(); break;
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case 0x58: cpu->sr.bits.i=0; incpc(); break;
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case 0xB8: cpu->sr.bits.v=0; incpc(); break;
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case 0x38: cpu->sr.bits.c=1; incpc(); break;
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case 0xF8: cpu->sr.bits.d=1; incpc(); break;
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case 0x78: cpu->sr.bits.i=1; incpc(); break;
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case 0x08: push( cpu->sr.reg ); incpc(); break;
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case 0x28: pull( &cpu->sr.reg ); incpc(); break;
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// ASL
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// TODO Move memory, not accumulator
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// TODO make sure zp/similar offsets are WRAPPED to 8-bits!
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case 0x0A: cpu->a = cpu->a << 1 ; incpc(); break;
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case 0x06: asl( ( fetch() ) ); incpc(); break;
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case 0x16: asl( ( fetch() + cpu->x ) ); incpc(); break;
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case 0x0E: asl( ( fetch16() ) ); incpc(); break;
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case 0x1E: asl( ( fetch16() + cpu->x ) ); incpc(); break;
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// LSR
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// TODO Move memory, not accumulator
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// TODO make sure zp/similar offsets are WRAPPED to 8-bits!
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case 0x4A: cpu->a = cpu->a >> 1; incpc(); break;
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case 0x46: lsr( fetch() ); incpc(); break;
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case 0x56: lsr( fetch() + cpu->x ); incpc(); break;
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case 0x4E: lsr( fetch16() ); incpc(); break;
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case 0x5E: lsr( fetch16() + cpu->x ); incpc(); break;
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// Jump/branch ---
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case 0x4C: ldpc( fetch16() ); break;
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case 0x6C: ldpc( deref( fetch16() ) ); break;
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case 0x20: push16( cpu->pc + 3 ); ldpc( fetch16() ); break;
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case 0xF0: ( cpu->sr.bits.z ) ? ( ldpc( cpu->pc + (int8_t)fetch() ) ) : ( 0 ); incpc(); incpc(); break;
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case 0xD0: ( !cpu->sr.bits.z ) ? ( ldpc( cpu->pc + (int8_t)fetch() ) ) : ( 0 ); incpc(); incpc(); break;
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case 0xB0: ( cpu->sr.bits.c ) ? ( ldpc( cpu->pc + (int8_t)fetch() ) ) : ( 0 ); incpc(); incpc(); break;
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case 0x90: ( !cpu->sr.bits.c ) ? ( ldpc( cpu->pc + (int8_t)fetch() ) ) : ( 0 ); incpc(); incpc(); break;
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// Comparison ---
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case 0xC9: cmp( cpu->a, fetch() ); incpc(); break;
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case 0xC5: cmp( cpu->a, deref( fetch() ) ); incpc(); break;
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case 0xD5: cmp( cpu->a, deref( fetch() + cpu->x ) ); incpc(); break;
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case 0xCD: cmp( cpu->a, deref( fetch16() ) ); incpc(); break;
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case 0xDD: cmp( cpu->a, deref( fetch16() + cpu->x ) ); incpc(); break;
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case 0xD9: cmp( cpu->a, deref( fetch16() + cpu->x ) ); incpc(); break;
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case 0xC1: cmp( cpu->a, deref( deref( fetch() + cpu->x ) ) ); incpc(); break;
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case 0xD1: cmp( cpu->a, deref( deref( fetch() + cpu->y ) ) ); incpc(); break;
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case 0xE0: cmp( cpu->x, fetch() ); incpc(); break;
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case 0xE4: cmp( cpu->x, deref( fetch() ) ); incpc(); break;
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case 0xEC: cmp( cpu->x, deref( fetch16() ) ); incpc(); break;
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case 0xC0: cmp( cpu->y, fetch() ); incpc(); break;
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case 0xC4: cmp( cpu->y, deref( fetch() ) ); incpc(); break;
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case 0xCC: cmp( cpu->y, deref( fetch16() ) ); incpc(); break;
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// Return ---
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case 0x60: pull16( &cpu->pc ); break;
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// Misc ---
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case 0xEA: nop(); incpc(); break;
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case 0x00: brk(); incpc(); break;
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default: incpc(); break;
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}
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}
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