cpu/disasm: LSR addressing modes fixed
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9ef3039d3d
commit
b4578c1900
14
Makefile
14
Makefile
@ -4,19 +4,15 @@ AS65FLAGS= -C
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PROG= 65
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OBJS= 65.o cpu.o ram.o rom.o disasm.o
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TESTDIR= test
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TESTOBJS= nes.nes asciitest.nes
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CFLAGS = -Wfatal-errors
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LDFLAGS += -lncurses
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$(PROG): $(OBJS)
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$(CC) $(OBJS) -o $(PROG) $(CFLAGS) $(LDFLAGS)
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test: $(foreach x,$(TESTOBJS),$(TESTDIR)/$(x))
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cp $(TESTDIR)/*.nes .
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.a65.nes:
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$(AS65) $(AS65FLAGS) $*.a65 -o $*.nes
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test:
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make -C test
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clean:
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$(RM) *.o $(TESTDIR)/*.nes $(PROG) $(TESTOBJS)
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$(RM) *.o $(PROG)
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make clean -C test
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.SUFFIXES: .nes .o65 .a65
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.PHONY: all clean tests
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.PHONY: all clean test
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25
cpu.c
25
cpu.c
@ -85,8 +85,8 @@ void cpu_exec(cpu_t*cpu,ram_t*ram)
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case 0x7D: adc( deref( fetch16() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0x79: adc( deref( fetch16() + cpu->y ) ); sr_nz(cpu->a); incpc(); break;
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// TODO Verify these are correct (use ind() )
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case 0x61: adc( ind( fetch() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0x71: adc( ind( fetch() + cpu->y ) ); sr_nz(cpu->a); incpc(); break;
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case 0x61: adc( deref( fetch() + cpu->x ) ); sr_nz(cpu->a); incpc(); break;
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case 0x71: adc( deref( fetch() + cpu->y ) ); sr_nz(cpu->a); incpc(); break;
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// INC/DEC
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case 0xE8: cpu->x += 1; incpc(); break;
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@ -132,15 +132,24 @@ void cpu_exec(cpu_t*cpu,ram_t*ram)
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// ASL
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// TODO Move memory, not accumulator
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// TODO make sure zp/similar offsets are WRAPPED to 8-bits!
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case 0x0A: asl( cpu->a ); incpc(); break;
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case 0x06: asl( deref( fetch() ) ); incpc(); break;
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case 0x16: asl( deref( fetch() + cpu->x ) ); incpc(); break;
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case 0x0E: asl( deref( fetch16() ) ); incpc(); break;
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case 0x1E: asl( deref( fetch16() + cpu->x ) ); incpc(); break;
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case 0x0A: cpu->a = cpu->a << 1 ; incpc(); break;
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case 0x06: asl( ( fetch() ) ); incpc(); break;
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case 0x16: asl( ( fetch() + cpu->x ) ); incpc(); break;
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case 0x0E: asl( ( fetch16() ) ); incpc(); break;
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case 0x1E: asl( ( fetch16() + cpu->x ) ); incpc(); break;
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// LSR
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// TODO Move memory, not accumulator
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// TODO make sure zp/similar offsets are WRAPPED to 8-bits!
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case 0x4A: cpu->a = cpu->a >> 1; incpc(); break;
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case 0x46: lsr( fetch() ); incpc(); break;
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case 0x56: lsr( fetch() + cpu->x ); incpc(); break;
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case 0x4E: lsr( fetch16() ); incpc(); break;
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case 0x5E: lsr( fetch16() + cpu->x ); incpc(); break;
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// Jump/branch ---
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case 0x4C: ldpc( fetch16() ); break;
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case 0x6C: ldpc( ind( fetch16() ) ); break;
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case 0x6C: ldpc( deref( fetch16() ) ); break;
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case 0xEA: nop(); incpc(); break;
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case 0x00: brk(); incpc(); break;
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default: incpc(); break;
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20
cpu.h
20
cpu.h
@ -46,7 +46,7 @@ typedef struct cpu_t
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// General purpose "micro-insns"/macros
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#define __cpu cpu
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#define incpc fetch
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#define incpc() (__cpu->pc+=1)
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#define fetch() (ram->ram[cpu_fetch(__cpu)]) // Get immediate binary value
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#define fetch16() ( fetch() | (fetch()<<8) ) // Get immediate 16-bit binary value
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#define deref(x) (ram_indirect_address(ram,x))
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@ -54,11 +54,8 @@ typedef struct cpu_t
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// Addressing mode "micro-insns"
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#define imm fetch
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#define imm16 fetch16 // Get immediate 16-bit binary value
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#define zp fetch // Get value at $0000 + x
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#define ab imm16 // Get 16-bit address
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#define ind(x) ram_indirect_address(ram,x)
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#define xidx(z) (__cpu->x+z) // Get value at y + (m)
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#define yidx(z) (__cpu->y+z) // Get value at x + (m)
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//#define zp fetch // Get value at $0000 + x
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//#define ab imm16 // Get 16-bit address
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// Peek (without fetching)
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#define imm_pk(x) (ram->ram[__cpu->pc+x]) // Peek immediate
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@ -76,10 +73,13 @@ typedef struct cpu_t
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// Arithmetic micro-insns
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#define adc(x) (cpu_adc(__cpu,x))
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// TODO AND is not always for accumulator
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#define and(x) (__cpu->a &= x)
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#define eor(x) (__cpu->a ^= x)
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#define ora(x) (__cpu->a |= x)
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#define asl(x) (__cpu->a = x<<1)
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#define and(x) (__cpu->a &= (x))
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#define eor(x) (__cpu->a ^= (x))
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#define ora(x) (__cpu->a |= (x))
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#define asl(x) (ram_asl(ram,(x)))
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#define lsr(x) (ram_lsr(ram,(x)))
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//#define asl(z) (z = z << 1)
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//#define lsr(z) (z = z >> 1)
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// Status register micro-insns
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#define sr_n(x) (__cpu->sr.bits.n=(x<0)) // Negative
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7
disasm.c
7
disasm.c
@ -176,6 +176,13 @@ void da_print_disassembly(cpu_t*cpu,ram_t*ram)
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case 0x0E: p3( "asl abs $%04X", imm16_pk(1) ); end();
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case 0x1E: p3( "asl abs $%04X,x", imm16_pk(1) ); end();
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// LSR
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case 0x4A: p1( "lsr a" ); end();
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case 0x46: p2( "lsr zp $%02X", imm_pk(1) ); end();
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case 0x56: p2( "lsr zp $%02X,x", imm_pk(1) ); end();
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case 0x4E: p3( "lsr abs $%04X", imm16_pk(1) ); end();
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case 0x5E: p3( "lsr abs $%04X,x", imm16_pk(1) ); end();
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// Jump/branch
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case 0x4C: p3( "jmp abs $%04X", imm16_pk(1) ); end();
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case 0x6C: p3( "jmp ind ($%04X) <%04X>", imm16_pk(1), *(uint16_t*)(ram->ram+imm16_pk(1)) ); end();
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12
ram.c
12
ram.c
@ -18,6 +18,18 @@ ram_t*ram_init(void)
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return ram;
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}
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// Arithmetic Shift Left
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void ram_asl(ram_t*ram,uint16_t byte)
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{
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ram->ram[byte]=ram->ram[byte]<<1;
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}
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// Logical Shift Right
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void ram_lsr(ram_t*ram,uint16_t byte)
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{
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ram->ram[byte]=ram->ram[byte]>>1;
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}
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// Free data belonging to ram object
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void ram_del(ram_t*ram)
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{
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2
ram.h
2
ram.h
@ -17,3 +17,5 @@ typedef struct ram_t
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ram_t*ram_init(void);
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void ram_del(ram_t*ram);
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uint16_t ram_indirect_address(ram_t*ram,uint16_t src);
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void ram_asl(ram_t*ram,uint16_t byte);
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void ram_lsr(ram_t*ram,uint16_t byte);
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@ -1,11 +1,12 @@
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AS65= xa
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AS65FLAGS= -C
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OBJS= nes.nes asciitest.nes
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OBJS= nes.nes asciitest.nes asl.nes
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all: $(OBJS)
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.a65.nes:
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$(AS65) $(AS65FLAGS) $*.a65 -o $*.nes
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cp $*.nes ..
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clean:
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$(RM) $(OBJS)
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.SUFFIXES: .a65 .nes
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