cpu/disasm: LSR addressing modes fixed

Makefile

@@ -4,19 +4,15 @@ AS65FLAGS= -C
 PROG= 65
 OBJS= 65.o cpu.o ram.o rom.o disasm.o
 
-TESTDIR= test
-TESTOBJS= nes.nes asciitest.nes
-
 CFLAGS = -Wfatal-errors
 LDFLAGS += -lncurses
 
 $(PROG): $(OBJS)
 	$(CC) $(OBJS) -o $(PROG) $(CFLAGS) $(LDFLAGS)
-test: $(foreach x,$(TESTOBJS),$(TESTDIR)/$(x))
-	cp $(TESTDIR)/*.nes .
-.a65.nes:
-	$(AS65) $(AS65FLAGS) $*.a65 -o $*.nes
+test:
+	make -C test
 clean:
-	$(RM) *.o $(TESTDIR)/*.nes $(PROG) $(TESTOBJS)
+	$(RM) *.o $(PROG)
+	make clean -C test
 .SUFFIXES: .nes .o65 .a65
-.PHONY: all clean tests
+.PHONY: all clean test

cpu.c

@@ -85,8 +85,8 @@ void cpu_exec(cpu_t*cpu,ram_t*ram)
 		case 0x7D: adc( deref( fetch16() + cpu->x ) );			sr_nz(cpu->a);	incpc();	break;
 		case 0x79: adc( deref( fetch16() + cpu->y ) );			sr_nz(cpu->a);	incpc();	break;
 		// TODO Verify these are correct (use ind() )
-		case 0x61: adc( ind( fetch() + cpu->x ) );			sr_nz(cpu->a);	incpc();	break;
-		case 0x71: adc( ind( fetch() + cpu->y ) );			sr_nz(cpu->a);	incpc();	break;
+		case 0x61: adc( deref( fetch() + cpu->x ) );			sr_nz(cpu->a);	incpc();	break;
+		case 0x71: adc( deref( fetch() + cpu->y ) );			sr_nz(cpu->a);	incpc();	break;
 
 		// INC/DEC
 		case 0xE8: cpu->x += 1;		incpc();		break;
@@ -132,15 +132,24 @@ void cpu_exec(cpu_t*cpu,ram_t*ram)
 		// ASL
 		// TODO Move memory, not accumulator
 		// TODO make sure zp/similar offsets are WRAPPED to 8-bits!
-		case 0x0A: asl( cpu->a ); incpc(); break;
-		case 0x06: asl( deref( fetch() ) ); incpc(); break;
-		case 0x16: asl( deref( fetch() + cpu->x ) ); incpc(); break;
-		case 0x0E: asl( deref( fetch16() ) ); incpc(); break;
-		case 0x1E: asl( deref( fetch16() + cpu->x ) ); incpc(); break;
+		case 0x0A: cpu->a = cpu->a << 1 ; incpc(); break;
+		case 0x06: asl( ( fetch() ) ); incpc(); break;
+		case 0x16: asl( ( fetch() + cpu->x ) ); incpc(); break;
+		case 0x0E: asl( ( fetch16() ) ); incpc(); break;
+		case 0x1E: asl( ( fetch16() + cpu->x ) ); incpc(); break;
+
+		// LSR
+		// TODO Move memory, not accumulator
+		// TODO make sure zp/similar offsets are WRAPPED to 8-bits!
+		case 0x4A: cpu->a = cpu->a >> 1; incpc(); break;
+		case 0x46: lsr( fetch() ); incpc(); break;
+		case 0x56: lsr( fetch() + cpu->x ); incpc(); break;
+		case 0x4E: lsr( fetch16() ); incpc(); break;
+		case 0x5E: lsr( fetch16() + cpu->x ); incpc(); break;
 
 		// Jump/branch ---
 		case 0x4C: ldpc( fetch16() );				break;
-		case 0x6C: ldpc( ind( fetch16() ) );				break;
+		case 0x6C: ldpc( deref( fetch16() ) );				break;
 		case 0xEA: nop();			incpc();	break;
 		case 0x00: brk(); 			incpc();	break;
 		default: incpc();						break;

cpu.h

@@ -46,7 +46,7 @@ typedef struct cpu_t
 
 // General purpose "micro-insns"/macros
 #define __cpu cpu
-#define incpc		fetch
+#define incpc()		(__cpu->pc+=1)
 #define fetch()		(ram->ram[cpu_fetch(__cpu)])	// Get immediate binary value
 #define fetch16()	( fetch() | (fetch()<<8) )		// Get immediate 16-bit binary value
 #define deref(x)	(ram_indirect_address(ram,x))
@@ -54,11 +54,8 @@ typedef struct cpu_t
 // Addressing mode "micro-insns"
 #define imm			fetch
 #define imm16		fetch16							// Get immediate 16-bit binary value
-#define zp			fetch							// Get value at $0000 + x
-#define ab			imm16							// Get 16-bit address
-#define ind(x)		ram_indirect_address(ram,x)
-#define xidx(z)		(__cpu->x+z)						// Get value at y + (m)
-#define yidx(z)		(__cpu->y+z)						// Get value at x + (m)
+//#define zp			fetch							// Get value at $0000 + x
+//#define ab			imm16							// Get 16-bit address
 
 // Peek (without fetching)
 #define imm_pk(x)	(ram->ram[__cpu->pc+x])			// Peek immediate
@@ -76,10 +73,13 @@ typedef struct cpu_t
 // Arithmetic micro-insns
 #define adc(x)		(cpu_adc(__cpu,x))
 // TODO AND is not always for accumulator
-#define and(x)		(__cpu->a &= x)
-#define eor(x)		(__cpu->a ^= x)
-#define ora(x)		(__cpu->a |= x)
-#define asl(x)		(__cpu->a = x<<1)
+#define and(x)		(__cpu->a &= (x))
+#define eor(x)		(__cpu->a ^= (x))
+#define ora(x)		(__cpu->a |= (x))
+#define asl(x)		(ram_asl(ram,(x)))
+#define lsr(x)		(ram_lsr(ram,(x)))
+//#define asl(z)		(z = z << 1)
+//#define lsr(z)		(z = z >> 1)
 
 // Status register micro-insns
 #define sr_n(x)		(__cpu->sr.bits.n=(x<0)) 		// Negative

disasm.c

@@ -176,6 +176,13 @@ void da_print_disassembly(cpu_t*cpu,ram_t*ram)
 		case 0x0E: p3( "asl abs $%04X", imm16_pk(1) ); end();
 		case 0x1E: p3( "asl abs $%04X,x", imm16_pk(1) ); end();
 
+		// LSR
+		case 0x4A: p1( "lsr a" ); end();
+		case 0x46: p2( "lsr zp $%02X", imm_pk(1) ); end();
+		case 0x56: p2( "lsr zp $%02X,x", imm_pk(1) ); end();
+		case 0x4E: p3( "lsr abs $%04X", imm16_pk(1) ); end();
+		case 0x5E: p3( "lsr abs $%04X,x", imm16_pk(1) ); end();
+
 		// Jump/branch
 		case 0x4C: p3( "jmp abs $%04X", imm16_pk(1) ); end();
 		case 0x6C: p3( "jmp ind ($%04X) <%04X>", imm16_pk(1), *(uint16_t*)(ram->ram+imm16_pk(1)) ); end();

ram.c

@@ -18,6 +18,18 @@ ram_t*ram_init(void)
 	return ram;
 }
 
+// Arithmetic Shift Left
+void ram_asl(ram_t*ram,uint16_t byte)
+{
+	ram->ram[byte]=ram->ram[byte]<<1;
+}
+
+// Logical Shift Right
+void ram_lsr(ram_t*ram,uint16_t byte)
+{
+	ram->ram[byte]=ram->ram[byte]>>1;
+}
+
 // Free data belonging to ram object
 void ram_del(ram_t*ram)
 {

ram.h

@@ -17,3 +17,5 @@ typedef struct ram_t
 ram_t*ram_init(void);
 void ram_del(ram_t*ram);
 uint16_t ram_indirect_address(ram_t*ram,uint16_t src);
+void ram_asl(ram_t*ram,uint16_t byte);
+void ram_lsr(ram_t*ram,uint16_t byte);

test/Makefile

@@ -1,11 +1,12 @@
 AS65= xa
 AS65FLAGS= -C
 
-OBJS= nes.nes asciitest.nes
+OBJS= nes.nes asciitest.nes asl.nes
 
 all: $(OBJS)
 .a65.nes:
 	$(AS65) $(AS65FLAGS) $*.a65 -o $*.nes
+	cp $*.nes ..
 clean:
 	$(RM) $(OBJS)
 .SUFFIXES: .a65 .nes